This invention generally relates to the field of electrostatic discharge (ESD) protection circuitry, and more specifically, improvements for silicon controlled rectifier (SCR) circuits in the protection circuitry of an integrated circuit (IC).
Silicon controlled Rectifiers (SCRs) have long been used over a broad range of technologies because of their superior performance. During an ESD event, the SCR is considered a superior device because the SCR acts as an almost ideal shunt element.
One concern in the industry about using SCRs as ESD protection devices is unintentional latch-up during normal operating conditions. Latch-up is an uncontrolled triggering of an (parasitic) SCR structure on the IC during normal operation, such that the supply voltage is shorted to ground. The holding currents of such (parasitic) SCR structures are specified in the industry as the minimum latch-up current. Typical values are a minimum of 100 milliamps, or up to 300-500 milliamps under severe operating conditions. A latch-up condition could lead to very high currents from the power supply that may permanently damage the IC.
One method to avoid latch-up in the SCR ESD protection devices is to provide serial coupled diodes between, for example, a pad and the anode of the SCR, such that the holding voltage is kept above the supply voltage. In other words, when the holding voltage is above the supply voltage (including some safety margin), the risk of a latch-up condition is avoided. Generally, there is a tendency in the industry to use lower voltages to power the IC""s, yet there are circuit applications where even much higher voltages are required (e.g., automotive applications or IC""s for certain functions in cellular phones). Accordingly, the higher the supply voltage, the more series diodes are required.
The use of the series diodes with the SCR has several disadvantages. A first disadvantage for such a high holding voltage is that a considerable number of serial coupled diodes would be a needed, which requires additional area (i.e., real estate) on the IC. A second disadvantage is that the serial diodes do not add functionality to the circuits on the IC, except for increasing the holding voltage. A third disadvantage is that a large number of series diodes (e.g., greater than three) may result in high leakage currents, due to a parasitic Darlington transistor to the substrate that amplifies an initial leakage current and becomes more problematic at higher operating temperatures.
In particular, each serial diode forms a stage of the Darlington transistor, and the stages are connected such that the leakage current of one stage is being amplified by the next stage, and so forth. This is called the Darlington amplifier in standard circuit theory, and the more of these Darlington stages are coupled, the more leakage current is generated. Moreover, during high ambient or operating temperatures of the chip, the leakage current increases, because there is more thermal carrier generation. As such, the series diodes pose a strong limit to the application of the SCR devices for also satisfying the above-mentioned latch-up concern.
Therefore, there is a need in the art for an ESD protection device having a high immunity to a latch-up condition during normal operation of the circuit, while still being able to provide ESD protection to the IC circuitry.
The disadvantages heretofore associated with the prior art are overcome by various embodiments of an electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection circuit has a high holding current for latch-up immunity. In one embodiment, the ESD protection device includes a silicon controlled rectifier (SCR) coupled between a protected supply line of the IC and ground. A trigger device is coupled from the supply line to a first gate of the SCR, and a first substrate resistor is coupled between the first gate and ground. A first fixed shunt resistor is coupled between the first gate and ground, where the shunt resistor has a resistance value lower than the substrate resistor. During either a powered-on or powered-off IC state, the triggering and holding currents are above the specified latch-up current of the SCR.
In a second embodiment, the ESD protection device includes an SCR coupled between a protected supply line of the IC and ground. A trigger device is coupled from the supply line to a first gate of the SCR, and a first substrate resistor is coupled between the first gate and ground. A first variable shunt resistor is coupled between the first gate and ground, where the shunt resistor has a resistance value lower than the first substrate resistor. During a powered-on IC state, the triggering and holding currents are above the specified latch-up current of the SCR. However, during a powered-off IC state, the triggering current is below the specified latch-up current of the SCR.